AI-native workflows. Open standards. Reusable silicon IP.
Vyges makes chip design as fast and composable as software.
Vyges unifies reusable IP, metadata standards, and AI-powered design tools — creating the missing ecosystem layer for building silicon like software. Supporting ASIC and FPGA, digital and analog/mixed-signal IP, from open-source to commercial licensing.
First discoverable silicon IP registry catalog with standardized metadata and licensing
Vyges Metadata Specification enables seamless IP integration and automation
Build IP 60% faster with standardized templates and automated workflows
Built-in compliance, SBOM tracking, and standardized IP display
Supports analog and mixed-signal design — a key growth focus for the platform
From idea to silicon with shuttle programs, test chips, and fab support
Built for the open silicon ecosystem — from individual developers to global semiconductor teams.
Publish, discover, and manage reusable IP blocks with standardized metadata, licensing, and end-to-end validation support.
Accelerate IP development by 60% with trusted components, compliance tools, and shuttle programs for silicon validation.
Access open-source PDKs, standardized templates, and educational resources for teaching and research in silicon design.
Integrate with the Vyges ecosystem through standardized metadata and support both open-source and commercial IP flows.
Everything you need to design, validate, and discover hardware IP
Create new IP repositories with standardized templates for ASIC and FPGA
Start Building →Validate your IP repository for schema compliance and quality metrics
Check Your IP →From open-source to commercial licensing, Vyges supports the full spectrum of silicon development
🚧 Under Active Development: We're building this ecosystem in real-time. The IP catalog and additional features are being developed as we work with early partners and contributors.
Digital, analog, and mixed-signal designs with OpenLane, commercial tools, and multiple PDK support
Open-source and commercial toolchains with board-specific constraints and examples
Apache-2.0, MIT, CERN-OHL-S, and other open-source licenses with full source code access
Encrypted RTL, NDA protection, and flexible licensing models for proprietary IP
Start creating reusable IP blocks today with our standardized templates and tools
Start with our ASIC or FPGA templates that include the Vyges Metadata Specification
Develop your IP block with standardized structure and comprehensive documentation
Use our compliance checker and prepare for the upcoming IP catalog
Early contributors get special recognition and influence on platform direction